1. Field of the Invention
The present invention relates to control systems and, more particularly, to a clock generation system for generating a first clock signal at a first clock frequency and a second clock signal at a second clock frequency with a predetermined ratio to the first clock frequency.
2. Description of the Related Art
EP 2 207 263 A1 discloses a clock system that includes a clock signal generator providing a first clock signal at a first clock frequency f, a first frequency divider dividing the first clock frequency by a first integer N to produce a first auxiliary signal, a second frequency divider dividing a second clock frequency by a second integer K to produce a second auxiliary signal, a phase/period comparator generating an error signal by comparing the first and second auxiliary signals, and a voltage-controlled oscillator (VCO) controlled dependent on the error signal to generate the second clock signal at the second clock frequency K/N·f.
The phase/period comparator, voltage-controlled oscillator and second frequency divider form a phase-locked loop (PLL) which locks onto a multiple, K, of its input frequency f/N so that the ratio of the second and first clock frequencies is K/N.
In practice, the frequencies of the first and second clock frequencies may be only slightly different, e.g., 3.000000 MHz and 2.999970 MHz, which thereby requires the integer divisors N=300000 and K=299997. Accordingly, a major disadvantage of this conventional clock generation system may be a long response time because the frequency multiplication is performed by the PLL and each frequency adjustment can only be made after the two signals are checked around the coincidence moment when N periods of the first clock signal=K periods of the second clock signal. Several corrections are necessary to lock the PLL, and when large N and K divider ratios are required, it takes a very long time to bring the PLL into lock.